| 1. |
- Al Khatib, Iyad, et al.
(author)
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Hardware/Software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology
- 2007
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In: Transactions on High-Performance Embedded Architectures and Compilers I. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 9783540715276 ; , s. 239-258
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Conference paper (peer-reviewed)abstract
- The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.
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| 2. |
- Al-Khatib, Iyad, et al.
(author)
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Performance Analysis and Design Space Exploration for High-End Biomedical Applications : Challenges and Solutions
- 2007
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In: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis. - New York, NY, USA : ACM. - 9781595938244 ; , s. 217-226
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Conference paper (peer-reviewed)abstract
- High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.
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| 3. |
- Badlund, Per, et al.
(author)
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An analytical approach for dimensioning mixed traffic networks
- 2007
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In: NOCS 2007. - 9780769527734 ; , s. 215-215
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Conference paper (peer-reviewed)abstract
- We present an analytical method for analyzing and dimensioning a network based communication architecture. The method is based on the classic (a, p) network calculus. We use a TDMA approach for creating logically separated networks which makes statistical methods possible for calculations on Best Effort traffic, and supports implementation of Guaranteed Bandwidth services by using Virtual Circuits with Looped Containers.
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| 4. |
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| 5. |
- Grecu, Cristian, et al.
(author)
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Towards open network-on-chip benchmarks
- 2007
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In: NOCS 2007. ; , s. 205-212
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Conference paper (peer-reviewed)abstract
- Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite.
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| 6. |
- Henriksson, Tomas, et al.
(author)
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Network Calculus Applied to Verification of Memory Access Performance in SoCs
- 2007
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In: Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007. - 9781424416547 ; , s. 21-26
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Conference paper (peer-reviewed)abstract
- SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus to the verification of memory access latencies. Two novel network elements, packet stretcher and packet compressor, are used to model the SoC interconnect and DRAM controller. We further extend the flow concept with a degree and make use of the peak characteristics of a flow to tighten the bounds in the analysis. We present a video playback case study and show that the proposed application of network calculus allows us to statically verify that all requirements on memory access latency are fulfilled.
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| 7. |
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| 8. |
- Herrholz, Andreas, et al.
(author)
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The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems
- 2007
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In: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE. - 9781424410606 - 1424410606 ; , s. 396-401
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Conference paper (peer-reviewed)abstract
- Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.
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| 9. |
- Liu, Ming, et al.
(author)
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Hardware/Software co-design of a general-purpose computation platform in particle physics
- 2007
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In: ICFPT 2007. - 9781424414710 ; , s. 177-183
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Conference paper (peer-reviewed)abstract
- In this paper we present a hardware/software co-design based computation platform for online data processing in particle physics experiments. Our goal is to ease and accelerate the development and make it universal and scalable for multiple applications, on the premise of guaranteeing high communicating and processing capabilities. The entire computation network consists of quite a few interconnected compute nodes, each of which has multiple FPGAs to implement specific algorithms for data processing. High-speed communication features including RocketIO multi-gigabit transceiver and Gigabit Ethernet are supported by FPGAs to construct internal and external connections. An embedded Linux operating system is fitted on the PowerPC CPU core inside the Xilinx Virtex-4 FX FPGA. Thus programmers can access hardware resources via device drivers and write application programs to manage the system from the high level. Furthermore measurements have been executed using the development board to investigate both communicating and processing performances of the system. Results show that the computation platform is able to communicate at a UDP/IP data rate of around 400 Mbps per Ethernet link, and the event selection engine could process an event rate of 25%.
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| 10. |
- Lu, Zhonghai, et al.
(author)
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Admitting and ejecting flits in wormhole-switched networks on chip
- 2007
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In: Iet Computers and Digital Techniques. - : Institution of Engineering and Technology (IET). - 1751-8601. ; 1:5, s. 546-556
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Journal article (peer-reviewed)abstract
- Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirectly, techniques for admitting and ejecting flits exert a significant impact on network performance and switch cost. Different flit-admission and flit-ejection micro-architectures are investigated. In particular, for flit admission, a novel coupling scheme which binds a flit-admission queue with a physical channel (PC) is presented. This scheme simplifies the switch crossbar from 2p x p to (p + 1) x p, where p is the number of PCs per switch. For flit ejection, a p-sink model that uses only p flit sinks to eject flits is proposed. In contrast to an ideal ejection model which requires p . v flit sinks (v is the number of virtual channels per PC), the buffering cost of flit sinks becomes independent of v. The proposed flit-admission and flit-ejection schemes are evaluated with both uniform and locality traffic in a 2D 4 x 4 mesh network. The results show that both schemes do not degrade network performance in terms of average packet latency and throughput if the flit injection rate is slower than 0.57 flit/cycle/node.
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